Main Menu
  • Home
  • DBBC
    • Backend general features
    • System components
    • VLBI Back-end Implementation
    • DBBC Digital Receiver
  • Development team
  • Contacts
  • Registration
  • Links

output input clock board dbbc architecture fpga sampling core

Home DBBC Backend general features

DBBC VLBI Backend General Features

PDF | Print | E-mail
  • 4 RF/IF Input from 16 in a range up to 2.200 GHz

  • Four polarizations or bands available for a single group of 64 output data channel selection (2 VSI output connectors with at present 1 or 2 Gb/s each)

  • 1024 MHz sampling clock frequency

  • Channel bandwidth ranging between 500 KHz and 16 MHz, U&L

  • Some wider channel bandwidth: 32 and 512 MHz, I&Q

  • Tuning step less than 1 Hz

  • Multiple architecture using fully re-configurable FPGA CoreBoard

  • Modular realization for cascaded stack processing

 

Back

 

Copyright © 2009 - 2011 Hat-Lab. - All Rights Reserved.

Webmaster - P.R.Platania - Website Powered by Joomla!.